High-Level Methods for Hardware IP Protections: Solutions, Trends, and Challenges

Due to the globalization of the semiconductor supply chain, the security threats for the production of an integrated circuit (IC) and its intellectual property (IP) are becoming more and more critical for many fab-less design houses. Conversely, the protections for these threats are expensive, especially when introduced in the last stages of the design flow. In this paper, we discuss the approaches, the trends, and the associated challenges that can be applied in the early stages of the design, i.e., before logic synthesis. On one hand, these approaches can operate on more semantic information and offer more protection. On the other hand, they have more effects on the overall design and need to somehow 'predict' the effects on the final implementation

Towards High-Level Synthesis of Quantum Circuits

In recent years, there has been a proliferation of quantum algorithms, primarily due to their exponential speedup over their classical counterparts. Quantum algorithms find applications in various domains, including machine learning, molecular simulation, and cryptography. However, extensive knowledge of linear algebra and quantum mechanics are required to program a quantum computer, which might not be feasible for traditional software programmers. Moreover, current quantum programming paradigm is difficult to scale and integrate quantum circuits to achieve complex functionality. To this end, in this paper, we introduce QHLS, a quantum high-level synthesis (HLS) framework. To the best of our knowledge, this is the first HLS framework for quantum circuits. The proposed QHLS allows quantum programmers to start with high-level behavioral descriptions (e.g., C, C++) and automatically generate the corresponding quantum circuit; thus, reducing the complexity of programming a quantum computer. Our experimental results demonstrate the success of QHLS in translating high-level behavioral software programs containing arithmetic, logical, and conditional statements

Performance Modeling of Parallel Applications on MPSoCs

In this paper we present a new technique for automatically measuring the performance of tasks, functions or arbitrary parts of a program on a multiprocessor embedded system. The technique instruments the tasks described by OpenMP, used to represent the task parallelism, while ad hoc pragmas in the source indicate other pieces of code to profile. The annotations and the instrumentation are completely target-independent, so the same code can be measured on different target architectures, on simulators or on prototypes. We validate the approach on a single and on a dual LEON 3 platform synthesized on FPGA, demonstrating a low instrumentation overhead. We show how the information obtained with this technique can be easily exploited in a hardware/software design space exploration tool, by estimating, with good accuracy, the speed-up of a parallel application given the profiling on the single processor prototype

Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions

The speed-up estimation of parallelized code is crucial to efficiently compare different parallelization techniques or task graph transformations. Unfortunately, most of the time, during the parallelization of a specification, the information that can be extracted by profiling the corresponding sequential code (e.g. the most executed paths) are not properly taken into account. In particular, correlating sequential path profiling with the corresponding parallelized code can help in the identification of code hot spots, opening new possibilities for automatic parallelization. For this reason, starting from a well-known profiling technique, the Efficient Path Profiling, we propose a methodology that estimates the speed-up of a parallelized specification, just using the corresponding hierarchical task graph representation and the information coming from the dynamic profiling of the initial sequential specification. Experimental results show that the proposed solution outperforms existing approaches

Reconfigurable logic for hardware IP protection: Opportunities and challenges

Protecting the intellectual property (IP) of integrated circuit (IC) design is becoming a significant concern of fab-less semiconductor design houses. Malicious actors can access the chip design at any stage, reverse engineer the functionality, and create illegal copies. On the one hand, defenders are crafting more and more solutions to hide the critical portions of the circuit. On the other hand, attackers are designing more and more powerful tools to extract useful information from the design and reverse engineer the functionality, especially when they can get access to working chips. In this context, the use of custom reconfigurable fabrics has recently been investigated for hardware IP protection. This paper will discuss recent trends in hardware obfuscation with embedded FPGAs, focusing also on the open challenges that must be necessarily addressed for making this solution viable

Polyamide 11-Carbon Nanotubes Nanocomposites: Preliminary Investigation

The objective of this research is to develop an improved polyamide 11 (PA11) polymer with enhanced flame retardancy, thermal, and mechanical properties for selective laser sintering (SLS) rapid manufacturing. In the present study, a nanophase was introduced into polyamide 11 via twin screw extrusion. Arkema Rilsan® polyamide 11 molding polymer pellets were used with 1, 3, 5, and 7 wt% loadings of Arkema’s GraphistrengthTM multi-wall carbon nanotubes (MWNTs) to create a family of PA11-MWNT nanocomposites. Transmission electron microscopy and scanning electron microscopy were used to determine the degree and uniformity of dispersion. Injection molded test specimens were fabricated for physical, thermal, mechanical properties, and flammability measurements. Thermal stability of these polyamide 11-MWNT nanocomposites was examined by TGA. Mechanical properties such as ultimate tensile strength, rupture tensile strength, and elongation at rupture were measured. Flammability properties were also obtained using the UL 94 test method. All these different methods and subsequent polymer characteristics are discussed in this paper.Mechanical Engineerin

Intumescent Flame Retardant Polyamide 11 Nanocomposites

Current polyamide 11 and 12 are lacking in fire retardancy and high strength/high heat resistance characteristics for a plethora of fabricated parts that are desired and required for performance driven applications. The introduction of selected nanoparticles such as surface modified montmorillonite (MMT) clay or carbon nanofibers (CNFs), combined with a conventional intumescent flame retardant (FR) additive into the polyamide 11/polyamide 12 (PA11/PA12) by melt processing conditions has resulted in the preparation of a family of intumescent polyamide nanocomposites. These intumescent polyamide 11 and 12 nanocomposites exhibit enhanced polymer performance characteristics, i.e., fire retardancy, high strength and high heat resistance and are expected to expand the market opportunities for polyamide 11 and polyamide 12 polymer manufacturers. The objective of this research is to develop improved polyamide 11 and 12 polymers with enhanced flame retardancy, thermal, and mechanical properties for selective laser sintering (SLS) rapid manufacturing (RM). In the present study, a nanophase was introduced into the polyamide 11 and combining it with a conventional intumescent FR additive via twin screw extrusion. Arkema RILSAN® polyamide 11 molding polymer pellets were examined with two types of nanoparticles: chemically modified montmorillonite (MMT) organoclays, and carbon nanofibers (CNFs); and Clairant’s Exolit® OP 1230 intumescent FR additive were used to create a family of FR intumescent polyamide 11 nanocomposites. Transmission electron microscopy (TEM) was used to determine the degree of nanoparticles dispersion. Injection molded specimens were fabricated for physical, thermal, and flammability measurements. Thermal stability of these intumescent polyamide 11 nanocomposites was examined by TGA. Flammability properties were obtained using the Cone Calorimeter at an external heat flux of 35 kW/m 2 and UL 94 Test Method. Heat deflection temperatures (HDT) were also measured. TEM micrographs, physical, thermal, and flammability properties are presented. FR intumescent polyamide 11 nanocomposites properties are compared with polyamide 11 baseline polymer. Based on flammability and mechanical material performance, selective polymers including polyamide 11 nanocomposites and control polyamide 11 will be cryogenically ground into fine powders for SLS RM processing. SLS specimens will be fabricated for thermal, flammability, and mechanical properties characterization.Mechanical Engineerin

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

To exploit the power of modern heterogeneous multiprocessor embedded platforms on partitioned applications, the designer usually needs to efficiently map and schedule all the tasks and the communications of the application, respecting the constraints imposed by the target architecture. Since the problem is heavily constrained, common methods used to explore such design space usually fail, obtaining low-quality solutions. In this paper, we propose an ant colony optimization (ACO) heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. We compare our approach with several other heuristics, including simulated annealing, tabu search, and genetic algorithms, on the performance to reach the optimum value and on the potential to explore the design space. We show that our approach obtains better results than other heuristics by at least 16% on average, despite an overhead in execution time. Finally, we validate the approach by scheduling and mapping a JPEG encoder on a realistic target architecture

Invited: High-level design methods for hardware security: Is it the right choice?

Due to the globalization of the electronics supply chain, hardware engineers are increasingly interested in modifying their chip designs to protect their intellectual property (IP) or the privacy of the final users. However, the integration of state-of-the-art solutions for hardware and hardware-assisted security is not fully automated, requiring the amendment of stable tools and industrial toolchains. This significantly limits the application in industrial designs, potentially affecting the security of the resulting chips. We discuss how existing solutions can be adapted to implement security features at higher levels of abstractions (during high-level synthesis or directly at the register-transfer level) and complement current industrial design and verification flows. Our modular framework allows designers to compose these solutions and create additional protection layers